The present invention relates to a method for regulating the decision threshold and/or the phase of a sampling clock signal of a data regenerator for a binary signal by evaluation of error correction signals.
Numerous circuits are known in which the decision threshold of a data regenerator and the phase of the sampling clock signal are corrected on the basis of criteria which are obtained from the received signal. In addition, there is a further group of data regenerators which, in the case of a redundant binary signal, utilize the error detection/error correction for controlling the decision threshold and the phase angle.
The published patent application DE 197 17 642 A1 discloses a method in which the decision threshold and the phase are varied with the aid of a control until the error rate reaches a minimum. In this method, the phase angle and the threshold always hunt around the optimum.
The U.S. Pat. No. 4,360,926 discloses a digital PLL (phase-locked loop) in which a phase comparison is carried out between the received signal and the sampling clock signal and, in addition, information of the error detector is used for optimization.
It is an object of the present invention, therefore, to develop a method and system for optimizing the decision threshold and/or the phase angle of the sampling clock signal.